Temperature-Sensitive Loop Parallelization for Chip Multiprocessors

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	Similar Articles Articles by Sri Hari Krishna Narayanan Articles by Guilin Chen Articles by Mahmut x Mahmut Kandemir, Articles by Yuan Xie

2005 International Conference on Computer Design

San Jose, California

October 02-October 05

ISBN: 0-7695-2451-6

	ASCII Text	x
	Sri Hari Krishna Narayanan, Guilin Chen, Mahmut x Mahmut Kandemir,, Yuan Xie, "Temperature-Sensitive Loop Parallelization for Chip Multiprocessors," Computer Design, International Conference on, pp. 677-682, 2005 International Conference on Computer Design, 2005.

	BibTex	x
	@article{ 10.1109/ICCD.2005.105, author = {Sri Hari Krishna Narayanan and Guilin Chen and Mahmut x Mahmut Kandemir, and Yuan Xie}, title = {Temperature-Sensitive Loop Parallelization for Chip Multiprocessors}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2005}, isbn = {0-7695-2451-6}, pages = {677-682}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.105}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - Temperature-Sensitive Loop Parallelization for Chip Multiprocessors SN - 0-7695-2451-6 SP677 EP682 A1 - Sri Hari Krishna Narayanan, A1 - Guilin Chen, A1 - Mahmut x Mahmut Kandemir,, A1 - Yuan Xie, PY - 2005 KW - null VL - 0 JA - Computer Design, International Conference on ER -

Sri Hari Krishna Narayanan, Department of CSE, The Pennsylvania State University

Guilin Chen, Department of CSE, The Pennsylvania State University

Mahmut x Mahmut Kandemir,, Department of CSE, The Pennsylvania State University

Yuan Xie, Department of CSE, The Pennsylvania State University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.105

In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9 degree C (4.3 degree C) when averaged over all the applications tested, incurring small performance/power penalties.

Citation:

Sri Hari Krishna Narayanan, Guilin Chen, Mahmut x Mahmut Kandemir,, Yuan Xie, "Temperature-Sensitive Loop Parallelization for Chip Multiprocessors," iccd, pp.677-682, 2005 International Conference on Computer Design, 2005

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