A High Performance Sub-Pipelined Architecture for AES

I
ICCD
2005
2005 International Conference on Computer Design
Abstract - A High Performance Sub-Pipelined Architecture for AES

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2005 International Conference on Computer Design

San Jose, California

October 02-October 05

ISBN: 0-7695-2451-6

	ASCII Text	x
	Hua Li, Jianzhou Li, "A High Performance Sub-Pipelined Architecture for AES," Computer Design, International Conference on, pp. 491-496, 2005 International Conference on Computer Design, 2005.

	BibTex	x
	@article{ 10.1109/ICCD.2005.10, author = {Hua Li and Jianzhou Li}, title = {A High Performance Sub-Pipelined Architecture for AES}, journal ={Computer Design, International Conference on}, volume = {0}, year = {2005}, isbn = {0-7695-2451-6}, pages = {491-496}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.10}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - A High Performance Sub-Pipelined Architecture for AES SN - 0-7695-2451-6 SP491 EP496 A1 - Hua Li, A1 - Jianzhou Li, PY - 2005 KW - AES KW - sub-pipelined architecture KW - FPGA KW - cryptography VL - 0 JA - Computer Design, International Conference on ER -

Hua Li, Department of Mathematics and Computer Science, University of Lethbridge

Jianzhou Li, Department of Mathematics and Computer Science, University of Lethbridge

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.2005.10

In this paper, an efficient sub-pipelined architecture for AES is proposed. It can do both encryption and decryption with well evenly divided three-stage pipeline. The threestage pipelined key expansion module generates the corresponding subkeys concurrently for encryption or decryption. The design can operate in CBCk mode and process three blocks of data simultaneously. The proposed architecture is simulated in Verilog HDL and implemented using Xilinx Virtex II FPGA device. The comparison indicates that our design has a relatively low area and high throughput up to 1.57Gbits/s.

Index Terms:

AES, sub-pipelined architecture, FPGA, cryptography

Citation:

Hua Li, Jianzhou Li, "A High Performance Sub-Pipelined Architecture for AES," iccd, pp.491-496, 2005 International Conference on Computer Design, 2005

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