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2004 IEEE International Conference on Computer Design (ICCD'04)
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
San Jose, CA
October 11-October 13
ISBN: 0-7695-2231-9
Yinghua Li, UC Berkeley, Berkeley, CA
Rajeev Murgai, Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Takashi Miyoshi, Fujitsu Laboratories of America, Inc., Sunnyvale, CA
Ashwini Verma, Amdocs, San Jose, CA
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDelay methodology, vis-a-vis other approaches, is its high delay computation accuracy. It deliberately avoids the use of approximate models for cells and nets and interconnect reductions. XTalkDelay employs a path-based approach; uses detailed and accurate distributed RC parasitics for critical nets and their aggressors; uses BSIM3-accurate gate models; and invokes HSPICE for delay computation using only the minimum required set of input patterns. XTalkDelay has been successfully applied on two industrial designs.
Citation:
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma, "XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs," iccd, pp.208-215, 2004 IEEE International Conference on Computer Design (ICCD'04), 2004
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