2003 IEEE International Conference on Computer Design (ICCD'03) Power-Time Tradeoff in Test Scheduling for SoCs San Jose, California October 13-October 15 ISBN: 0-7695-2025-1
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use the power profile of non-embedded cores to find the best mix of their test pattern subsets that satisfy the power and/or time constraints. An MILP formulation is presented to globally perform the power-time tradeoff and produce the SoC test schedule. Many constraints including peak/average power of cores, time/sequencing requirements, and ATE pin limitation are also incorporated within this formulation.
Citation:
Mehrdad Nourani, James Chin, "Power-Time Tradeoff in Test Scheduling for SoCs," iccd, pp.548, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||