2003 IEEE International Conference on Computer Design (ICCD'03) Power Efficient Data Cache Designs San Jose, California October 13-October 15 ISBN: 0-7695-2025-1
This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different threshold voltages with different cache organizations that provide different levels of performance. Multi-banked organizations in combination with different approaches to allocate data to cache banks are explored. Some of the resulting cache architectures are shown to provide a good tradeoff between power and performance.
Citation:
Jaume Abella, Antonio Gonz?lez, "Power Efficient Data Cache Designs," iccd, pp.8, 2003 IEEE International Conference on Computer Design (ICCD'03), 2003 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||