2002 IEEE International Conference on Computer Design (ICCD'02) Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction Freiburg, Germany September 16-September 18 ISBN: 0-7695-1700-5
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for evaluating the effectiveness of each of these approaches independently and in conjunction with each other. Results show the advantages of multiple supply, transistor sizing, and multiple threshold can be compounded to maximize power reduction. The order of application of these techniques determines the final savings in active and leakage power.
Citation:
Stephanie Augsburger, Borivoje Nikolić, "Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction," iccd, pp.316, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||