2002 IEEE International Conference on Computer Design (ICCD'02) Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing Freiburg, Germany September 16-September 18 ISBN: 0-7695-1700-5
This paper presents a novel delay-insensitive three dimension pipeline array multiplier. The organization combines deep (gate-Ievel) pipelining of Manchester adders with two dimensional cross-pipeline mesh for multiplicand and multiplier propagation and partial product bits calculation. Fine grain pipelining with elimination of broadcasting and completion trees leads to high-throughput without use of dynamic logic that leaves the door open for further improvement ofperformance.
Citation:
Alexander Taubin, Karl Fant, John McCardle, "Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing," iccd, pp.104, 2002 IEEE International Conference on Computer Design (ICCD'02), 2002 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||