A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing

I
ICCD
1999
1999 IEEE International Conference on Computer Design (ICCD'99)
Abstract - A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing

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1999 IEEE International Conference on Computer Design (ICCD'99)

Austin, Texas

October 10-October 13

ISBN: 0-7695-0406-X

	ASCII Text	x
	Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada, "A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing," Computer Design, International Conference on, pp. 279, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.

	BibTex	x
	@article{ 10.1109/ICCD.1999.808438, author = {Kentaro Shimada and Tatsuya Kawashimo and Makoto Hanawa and Ryo Yamagata and Eiki Kamada}, title = {A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing}, journal ={Computer Design, International Conference on}, volume = {0}, year = {1999}, issn = {1063-6404}, pages = {279}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808438}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing SN - 1063-6404 SP EP A1 - Kentaro Shimada, A1 - Tatsuya Kawashimo, A1 - Makoto Hanawa, A1 - Ryo Yamagata, A1 - Eiki Kamada, PY - 1999 KW - supercomputer KW - scientific processing KW - slide-windowed registers KW - software prefetch KW - large number of FPRs KW - SR8000 VL - 0 JA - Computer Design, International Conference on ER -

Kentaro Shimada, Hitachi Limited

Tatsuya Kawashimo, Hitachi Limited

Makoto Hanawa, Hitachi Limited

Ryo Yamagata, Hitachi Limited

Eiki Kamada, Hitachi Limited

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808438

We have developed a superscalar RISC processor for the super technical server HITACHI SR8000. The processor includes architectural features specialized in scientific applications, in which massive amounts of data in the main memory must be processed. These features are a slide-windowed-registers scheme and a simultaneous execution of up to 16 prefetch instructions. The slide-windowed-registers scheme enables instructions of the processor to access any of 160 floating point registers (FPRs). The execution mechanism for prefetch instructions produces high efficiency of the out-of-order super-scalar processor despite the long latency of the main memory. A logic simulation showed that the performance of the processor reaches over 3 floating-point operations per cycle and the memory throughput of over 12 bytes per cycle.

Index Terms:

supercomputer, scientific processing, slide-windowed registers, software prefetch, large number of FPRs, SR8000

Citation:

Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada, "A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing," iccd, pp.279, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999

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