High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection

I
ICCD
1999
1999 IEEE International Conference on Computer Design (ICCD'99)
Abstract - High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Jae hun Choi Articles by Jae-Hyuck Kwak Articles by Earl E. Swartzlander, Jr.

1999 IEEE International Conference on Computer Design (ICCD'99)

Austin, Texas

October 10-October 13

ISBN: 0-7695-0406-X

	ASCII Text	x
	Jae hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander, Jr., "High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection," Computer Design, International Conference on, pp. 68, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999.

	BibTex	x
	@article{ 10.1109/ICCD.1999.808388, author = {Jae hun Choi and Jae-Hyuck Kwak and Earl E. Swartzlander, Jr.}, title = {High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection}, journal ={Computer Design, International Conference on}, volume = {0}, year = {1999}, issn = {1063-6404}, pages = {68}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808388}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Design, International Conference on TI - High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection SN - 1063-6404 SP EP A1 - Jae hun Choi, A1 - Jae-Hyuck Kwak, A1 - Earl E. Swartzlander, Jr., PY - 1999 KW - Low latency CORDIC architecture KW - Area optimization KW - Folded-transistor design VL - 0 JA - Computer Design, International Conference on ER -

Jae hun Choi, University of Texas at Austin

Jae-Hyuck Kwak, University of Texas at Austin

Earl E. Swartzlander, Jr., University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICCD.1999.808388

This paper presents an architecture for accelerating CORDIC vectoring mode operations. The processing is sped up by overlapping redundant sum formation and selection of rotation direction. We analyze the latency time and area, and compare them with a conventional CORDIC implementation. The results show that the proposed scheme reduces not only the the latency but also the overall computation time. Thus, it achieves higher throughput in pipelining.

Index Terms:

Low latency CORDIC architecture, Area optimization, Folded-transistor design

Citation:

Jae hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander, Jr., "High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection," iccd, pp.68, 1999 IEEE International Conference on Computer Design (ICCD'99), 1999

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.