Delay optimization is a fundamental goal in logic synthesis. This paper presents gate duplication as a strategy for performance optimization. Many timing optimization strategies have been proposed over the past few years.In the past few years, the research community has looked at gate duplication extensively as a method of reducing the cut-set of partitions. The strength of gate duplication as a cut-set minimizng strategy has been demonstrated. However apllicability of this strategy in reducing the circuit delay has not been studied in detail. One of the few works is which addresses the gate duplication problem in a performance driven perspective.The global (pertaining to the whole circuit) delay optimization problem by gate duplication is NP-Complete. In this paper we prove the problem of partitioning a set of fanouts between a gate and it's replica (both gates have the same fanins) such that the required time constraint at the input pin is met, to be NP-Complete. Hence even the local optimization by gate duplication problem (formally defined later) is also NP-Complete. We then present an algorithm for gate duplication which is based on the dynamic programming approach. Since the problem of partitioning a set of fanouts between a node and it's replica is NP-Complete, we use a heuristic for making this decision which is optimial under specific conditions.