2010 IEEE 12th International Conference on High Performance Computing and Communications Insertion Tree Phasers: Efficient and Scalable Barrier Synchronization for Fine-Grained Parallelism Melbourne, Australia September 01-September 03 ISBN: 978-0-7695-4214-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HPCC.2010.30
This paper presents an algorithm and a data structure for scalable dynamic synchronization in fine-grained parallelism. The algorithm supports the full generality of phasers with dynamic, two-phase, and point-to-point synchronization. It retains the scalability of classical tree barriers, but provides unbounded dynamicity by employing a tailor-made insertion tree data structure. It is the first completely documented implementation strategy for a scalable phaser synchronization construct. Our evaluation shows that it can be used as a drop-in replacement for classic barriers without harming performance, despite its additional complexity and potential for performance optimizations. Furthermore, our approach overcomes performance and scalability limitations which have been present in other phaser proposals.
Index Terms:
Fine-grained parallelism, barriers, phasers, synchronization, many-core, data structures, trees, algorithms
Citation:
Stefan Marr, Stijn Verhaegen, Bruno De Fraine, Theo D'Hondt, Wolfgang De Meuter, "Insertion Tree Phasers: Efficient and Scalable Barrier Synchronization for Fine-Grained Parallelism," hpcc, pp.130-137, 2010 IEEE 12th International Conference on High Performance Computing and Communications, 2010 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||