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11th International Symposium on High-Performance Computer Architecture (HPCA'05)
Power Efficient Processor Architecture and The Cell Processor
San Francisco, California
February 12-February 16
ISBN: 0-7695-2275-0
ASCII Text
x 
 
H. Peter Hofstee, "Power Efficient Processor Architecture and The Cell Processor," High-Performance Computer Architecture, International Symposium on, pp. 258-262, 11th International Symposium on High-Performance Computer Architecture (HPCA'05), 2005.
 
 
BibTex
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@article{ 10.1109/HPCA.2005.26,
author = {H. Peter Hofstee},
title = {Power Efficient Processor Architecture and The Cell Processor},
journal ={High-Performance Computer Architecture, International Symposium on},
volume = {0},
year = {2005},
issn = {1530-0897},
pages = {258-262},
doi = {http://doi.ieeecomputersociety.org/10.1109/HPCA.2005.26},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - High-Performance Computer Architecture, International Symposium on
TI - Power Efficient Processor Architecture and The Cell Processor
SN - 1530-0897
SP258
EP262
A1 - H. Peter Hofstee,
PY - 2005
KW - null
VL - 0
JA - High-Performance Computer Architecture, International Symposium on
ER -
 
H. Peter Hofstee, IBM Server & Technology Group
This paper provides a background and rationale for some of the architecture and design decisions in the Cell processor, a processor optimized for compute-intensive and broadband rich media applications, jointly developed by Sony Group, Toshiba, and IBM.
Citation:
H. Peter Hofstee, "Power Efficient Processor Architecture and The Cell Processor," hpca, pp.258-262, 11th International Symposium on High-Performance Computer Architecture (HPCA'05), 2005
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