7th International Conference on Hybrid Intelligent Systems (HIS 2007) A Neuromorphic aVLSI network chip with configurable plastic synapses Kaiserslautern, Germany September 17-September 19 ISBN: 0-7695-2946-1
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HIS.2007.60
We describe and demonstrate the key features of a neu- romorphic, analog VLSI chip (termed F-LANN) hosting 128 integrate-and-fire (IF) neurons with spike-frequency adap- tation, and 16 384 plastic bistable synapses implementing a self-regulated form of Hebbian, spike-driven, stochastic plasticity. We were successfully able to test and verify the basic operation of the chip as well as its main new fea- ture, namely the synaptic configurability. This configura- bility enables us to configure each individual synapse as either excitatory or inhibitory and to receive either recur- rent input from an on-chip neuron or AER (Address Event Representation)-based input from an off-chip neuron. It?s also possible to set the initial state of each synapse as po- tentiated or depressed, and the state of each synapse can be read and stored on a computer. The main aim of this chip is to be able to efficiently perform associative learning ex- periments on a large number of synapses. In the future we would like to connect up multiple F-LANN chips together to be able to perform associative learning of natural stimulus sets.
Citation:
P. Camilleri, M. Giulioni, V. Dante, D. Badoni, G. Indiveri, B. Michaelis, J. Braun, P. del Giudice, "A Neuromorphic aVLSI network chip with configurable plastic synapses," his, pp.296-301, 7th International Conference on Hybrid Intelligent Systems (HIS 2007), 2007 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||