This paper introduces an optimized mapping methodology for mapping instruction sequences (ISs) onto EPOM-processor arrays. The new features of this mapping methodology result from a systematic specification and exploitation of both instruction and processor level parallelism : ultra-low granularity of ISs requires an allocation and sched uling of individual instructions onto the given processor array. Moreover, this mapping methodology is complete in the sense that it considers both processor arrary topolgy, array busbandwidths and processor resource constraints. The mapping methdolodgy is based on two concepts.1. instruction sequences (Is) : they represent a generalized form of directed cyclic graphs (DCGs) and allow to efficiently specify algorithm parallelism. Graph nodes represent instructions out of the instruction set of a target processor architecture [The96a] [The97a]. 2. the EPOM-processor architecture : it represents an optimized VLIW-processor architecture (in terms of cost and performance) for parallel implementation of ISs [The96a] and is especially suited for parallel image / signal processing [The95]. In this paper, special attention is paid to the optimization of the mapping process os ISs onto EPOM-processor arrays .. Algorithm execution time minimization is used as optimization goal. The mapping methodology is partially based on integer-linear-programming and heuristic techniques. The solution time complexity is substantially reduced by developing a two-phase hierarchical model, decoupling processor array allocation from subsequent scheduling. The efficiency of this mapping methodology has been validated through experimental results on ISs of well-known algorithm routines.