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Fifth International Conference on High Performance Computing
A Parallel Skeletonization Algorithm and its VLSI Architecture
Madras, India
December 17-December 20
ISBN: 0-8186-9194-8
ASCII Text
x 
 
N. Sudha, S. Nandi, "A Parallel Skeletonization Algorithm and its VLSI Architecture," High-Performance Computing, International Conference on, pp. 65, Fifth International Conference on High Performance Computing, 1998.
 
 
BibTex
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@article{ 10.1109/HIPC.1998.737972,
author = {N. Sudha and S. Nandi},
title = {A Parallel Skeletonization Algorithm and its VLSI Architecture},
journal ={High-Performance Computing, International Conference on},
volume = {0},
year = {1998},
issn = {1094-7256},
pages = {65},
doi = {http://doi.ieeecomputersociety.org/10.1109/HIPC.1998.737972},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - High-Performance Computing, International Conference on
TI - A Parallel Skeletonization Algorithm and its VLSI Architecture
SN - 1094-7256
SP
EP
A1 - N. Sudha,
A1 - S. Nandi,
PY - 1998
VL - 0
JA - High-Performance Computing, International Conference on
ER -
 
This paper presents a new algorithm to extract the skeleton and its Euclidean distance values from a binary image. A VLSI implementation of the algorithm in a locally connected cellular array is also given. The algorithm runs in O(n) time for an image of size nxn. The extracted skeleton reconstructs the objects in the image exactly.
Citation:
N. Sudha, S. Nandi, "A Parallel Skeletonization Algorithm and its VLSI Architecture," hipc, pp.65, Fifth International Conference on High Performance Computing, 1998
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