Recent microprocessors have been enhanced with media instruction sets for accelerating media algorithms. They exploit the fact that media algorithms have small data types, and widths much less than that of the processor. Current media instruction sets support only 8-, 16- and 32-bit sub-datatypes. This scheme is ineffecient in several applications where bit lengths of 9, 12 and so on are used. We need user programmable sub-datatype bit lengths. [Arbitary Precision Arithmetic -- SIMD Style, S. Balakrishnan and S.K. Nandy, VLSI98] discusses arbitrary boundary packed addition.Many media algorithms are based on multiply-accumulate algorithms. For full acceleration we also need arbitrary boundary packed multiplication. We present such a scheme based on Wallace tree multiplication. We also expand on [Arbitary Precision Arithmetic -- SIMD Style, S. Balakrishnan and S.K. Nandy, VLSI98] and provide a detailed treatment of the intermediate carries of sub-datatypes which were lost in the previous work. These carries could be used for saturation arithmetic and flow control.