Application-specific instruction set processor (ASIP) design is a promising approach for meeting the performance and cost goals of an embedded system. We have developed a new micro-architecture for automatically constructing ASIPs. This new architecture, called a wide counter-flow pipeline (WCFP), is based on the counter-flow pipeline (CFP). Our ASIP synthesis technique uses software pipelining and design-space exploration to generate a custom WCFP and instruction set for an embedded application. In this paper, we first present a brief sketch of WCFPs and our design strategy. Second, we describe a software infrastructure for prototyping WCFPs to evaluate design trade-offs. Finally, based on preliminary experiments using several kernel loops, we show that WCFPs achieve speedups of 1.8-6.6 over a general-purpose CFP.