Building the 4 Processor SB-PRAM Prototype

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30th Hawaii International Conference on System Sciences (HICSS) Volume 5: Advanced Technology Track

Building the 4 Processor SB-PRAM Prototype (PDF)

Maui, Hawaii

January 03-January 06

ISBN: 0-8186-7743-0

	ASCII Text	x
	Peter Bach, Michael Braun, Arno Formella, Jorg Friedrich, Thomas Grun, Cedric Lichtenau, "Building the 4 Processor SB-PRAM Prototype," Hawaii International Conference on System Sciences, vol. 5, pp. 14, 30th Hawaii International Conference on System Sciences (HICSS) Volume 5: Advanced Technology Track, 1997.

	BibTex	x
	@article{ 10.1109/HICSS.1997.663155, author = {Peter Bach and Michael Braun and Arno Formella and Jorg Friedrich and Thomas Grun and Cedric Lichtenau}, title = {Building the 4 Processor SB-PRAM Prototype}, journal ={Hawaii International Conference on System Sciences}, volume = {5}, year = {1997}, issn = {1060-3425}, pages = {14}, doi = {http://doi.ieeecomputersociety.org/10.1109/HICSS.1997.663155}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Hawaii International Conference on System Sciences TI - Building the 4 Processor SB-PRAM Prototype SN - 1060-3425 SP EP A1 - Peter Bach, A1 - Michael Braun, A1 - Arno Formella, A1 - Jorg Friedrich, A1 - Thomas Grun, A1 - Cedric Lichtenau, PY - 1997 KW - null VL - 5 JA - Hawaii International Conference on System Sciences ER -

Peter Bach, Universitat des Saarlandes, FB14 Informatik, 66041 Saarbrucken, Germany

Michael Braun, Universitat des Saarlandes, FB14 Informatik, 66041 Saarbrucken, Germany

Arno Formella, Universitat des Saarlandes, FB14 Informatik, 66041 Saarbrucken, Germany

Jorg Friedrich, Universitat des Saarlandes, FB14 Informatik, 66041 Saarbrucken, Germany

Thomas Grun, Universitat des Saarlandes, FB14 Informatik, 66041 Saarbrucken, Germany

Cedric Lichtenau, Universitat des Saarlandes, FB14 Informatik, 66041 Saarbrucken, Germany

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/HICSS.1997.663155

The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the address space, and combining in the butterfly network. We have built a first research prototype with 4 physical processors, thus 128 virtual processors, to demonstrate the feasibility of the concept.

The programming environment consists of a FORK compiler for specifying PRAM programs, an extended C compiler, and the P4 library. The machine runs a parallel operating system which provides program execution and I/O system calls. The SB-PRAM allows for efficient programs with predictable performance. Some examples are presented. The 4 processor prototype is the first step towards a 128 processor machine for which we are adapting the existing hardware.

Citation:

Peter Bach, Michael Braun, Arno Formella, Jorg Friedrich, Thomas Grun, Cedric Lichtenau, "Building the 4 Processor SB-PRAM Prototype," hicss, vol. 5, pp.14, 30th Hawaii International Conference on System Sciences (HICSS) Volume 5: Advanced Technology Track, 1997

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