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Ninth Great Lakes Symposium on VLSI
Memory Chip BIST Architecture
Ann Arbor, Michigan
March 04-March 06
ISBN: 0-7695-0104-4
Jacob Savir, New Jersey Institute of Technology
This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: 1. Can be used in both built-in mode and off chip/module mode. 2. Can be used to test and diagnose naked arrays. 3. Fault diagnosis is simple and is "free" for some faults during test. 4. Is never subject to aliasing. 5. Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. 6. If used as built-in feature, it does not slow down the normal operation of the array. 7. Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. 8. If used as a built-in feature, the hardware overhead is very low.
Citation:
Jacob Savir, "Memory Chip BIST Architecture," glsvlsi, pp.384, Ninth Great Lakes Symposium on VLSI, 1999
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