Ninth Great Lakes Symposium on VLSI Linear Transconductors Using Low Voltage Low Power Square-Law Cmos Cells Ann Arbor, Michigan March 04-March 06 ISBN: 0-7695-0104-4
Two transconductors composed of two square-law CMOS cells are introduced in this paper. The analysis of the cells is given. The transconductors operate in the saturation region with a fully balanced input signal. Simulations were done for 0.8pm n-well process using BSIM3 model parameters. The first circuit has a trade-off between low voltage operation and low power dissipation. The circuit has a cutoff frequency of 170MHz and Pdis=l.l7mW for a bias current of 120pA. The second transconductor has aimed to overcome the trade-off and to improve the performance; the circuit has a cutoff frequency of 236MHz and Pdis =1.74mW for the same bias current, however, it is possible to reduce the bias current, since the trade-off The transconductors have a THD of less then -56dB and -6OdB, respectively, for lMHz, 0.5V peak-to-peak sinusoidal input. A comparison between the two circuit performances is given.
Citation:
Tuna B. Taram, Mohammed Ismail, "Linear Transconductors Using Low Voltage Low Power Square-Law Cmos Cells," glsvlsi, pp.206, Ninth Great Lakes Symposium on VLSI, 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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