VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing

G
GLSVLSI
1999
Ninth Great Lakes Symposium on VLSI
Abstract - VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing

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	Similar Articles Articles by Aamir A. Farooqui Articles by Vojin G. Oklobdzija

Ninth Great Lakes Symposium on VLSI

Ann Arbor, Michigan

March 04-March 06

ISBN: 0-7695-0104-4

	ASCII Text	x
	Aamir A. Farooqui, Vojin G. Oklobdzija, "VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing," Great Lakes Symposium on VLSI, pp. 30, Ninth Great Lakes Symposium on VLSI, 1999.

	BibTex	x
	@article{ 10.1109/GLSV.1999.757370, author = {Aamir A. Farooqui and Vojin G. Oklobdzija}, title = {VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1999}, issn = {1066-1395}, pages = {30}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757370}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing SN - 1066-1395 SP EP A1 - Aamir A. Farooqui, A1 - Vojin G. Oklobdzija, PY - 1999 VL - 0 JA - Great Lakes Symposium on VLSI ER -

Aamir A. Farooqui, University of California at Davis

Vojin G. Oklobdzija, University of California at Davis and Integration Berkeley

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1999.757370

In this paper, design and VLSI Implementation of an Early Branch Prediction (EBP) circuit, based on a variation of Carry Look-ahead scheme is presented. The key features of this design are low area, high speed (2 ?log n/2 ? + 1), and high modularity. This design out performs all the EBP designs presented so far. For 64-bit word length the early branch prediction is obtained in 679 ps as simulated for 0.2- mm technology under typical conditions. Simulation and layout results for 0.2- mm CMOS technology show a 30% increase in speed with 25% decrease in area as compared, to recently published results.

Citation:

Aamir A. Farooqui, Vojin G. Oklobdzija, "VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing," glsvlsi, pp.30, Ninth Great Lakes Symposium on VLSI, 1999

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