A low power based system partitioning and binding technique for multi-chip module architectures

G
GLSVLSI
1997
7th Great Lakes Symposium on VLSI
Abstract - A low power based system partitioning and binding technique for multi-chip module architectures

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by R.V. Cherabuddi Articles by M.A. Bayoumi Articles by H. Krishnamurthy

7th Great Lakes Symposium on VLSI

Urbana, IL

March 13-March 15

ISBN: 0-8186-7904-2

	ASCII Text	x
	R.V. Cherabuddi, M.A. Bayoumi, H. Krishnamurthy, "A low power based system partitioning and binding technique for multi-chip module architectures," Great Lakes Symposium on VLSI, pp. 156, 7th Great Lakes Symposium on VLSI, 1997.

	BibTex	x
	@article{ 10.1109/GLSV.1997.580530, author = {R.V. Cherabuddi and M.A. Bayoumi and H. Krishnamurthy}, title = {A low power based system partitioning and binding technique for multi-chip module architectures}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1997}, issn = {1066-1395}, pages = {156}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580530}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - A low power based system partitioning and binding technique for multi-chip module architectures SN - 1066-1395 SP EP A1 - R.V. Cherabuddi, A1 - M.A. Bayoumi, A1 - H. Krishnamurthy, PY - 1997 KW - multichip modules; system partitioning; binding technique; multi-chip module architectures; high-level synthesis framework; MCM; switching activity; functional units; inter-chip buses; stochastic evolution based technique; benchmark designs VL - 0 JA - Great Lakes Symposium on VLSI ER -

R.V. Cherabuddi, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

M.A. Bayoumi, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

H. Krishnamurthy, Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580530

In this paper, we present a low power targeted high-level synthesis framework for the synthesis of Multi-Chip Modules (MCM). This new framework is based on minimizing the switching activity on the functional units as well as the inter-chip buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for system partitioning. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.

Index Terms:

multichip modules; system partitioning; binding technique; multi-chip module architectures; high-level synthesis framework; MCM; switching activity; functional units; inter-chip buses; stochastic evolution based technique; benchmark designs

Citation:

R.V. Cherabuddi, M.A. Bayoumi, H. Krishnamurthy, "A low power based system partitioning and binding technique for multi-chip module architectures," glsvlsi, pp.156, 7th Great Lakes Symposium on VLSI, 1997

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.