Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits

G
GLSVLSI
1996
6th Great Lakes Symposium on VLSI
Abstract - Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits

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	Similar Articles Articles by Sankaran M. Menon Articles by Anura P. Jayasumana Articles by Yashwant K. Malaiya

6th Great Lakes Symposium on VLSI

Ames, IA

March 22-March 23

ISBN: 0-8186-7502-0

	ASCII Text	x
	Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya, "Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits," Great Lakes Symposium on VLSI, pp. 0214, 6th Great Lakes Symposium on VLSI, 1996.

	BibTex	x
	@article{ 10.1109/GLSV.1996.497622, author = {Sankaran M. Menon and Anura P. Jayasumana and Yashwant K. Malaiya}, title = {Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1996}, isbn = {0-8186-7502-0}, pages = {0214}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497622}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits SN - 0-8186-7502-0 SP EP A1 - Sankaran M. Menon, A1 - Anura P. Jayasumana, A1 - Yashwant K. Malaiya, PY - 1996 VL - 0 JA - Great Lakes Symposium on VLSI ER -

Sankaran M. Menon, South Dakota School of Mines & Tech

Anura P. Jayasumana, Colorado State University

Yashwant K. Malaiya, Colorado State University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1996.497622

Combining the advantages of Bipolar and CMOS, BiCMOS is emerging as a major technology for high speed, high performance, digital and mixed signal applications. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. This paper presents effects of bridging faults affecting p-and n-parts. It is shown that bridging faults can be detected by IDDQ monitoring in BiCMOS devices. An input pattern classification scheme is presented for bridging faults. These classes of input patterns are then used to obtain test sets for bridging fault detection.

Citation:

Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya, "Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits," glsvlsi, pp.0214, 6th Great Lakes Symposium on VLSI, 1996

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