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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Using EDIF for software generation
The State University of New York at Buffalo
March 16-March 18
ISBN: 0-8186-7035-5
ASCII Text
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M.J. Van Der Westhuizen, R.G. Harley, D.C. Levy, D.R. Woodward, "Using EDIF for software generation," Great Lakes Symposium on VLSI, pp. 172, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/GLSV.1995.516047,
author = {M.J. Van Der Westhuizen and R.G. Harley and D.C. Levy and D.R. Woodward},
title = {Using EDIF for software generation},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {172},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516047},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Using EDIF for software generation
SN - 1066-1395
SP
EP
A1 - M.J. Van Der Westhuizen,
A1 - R.G. Harley,
A1 - D.C. Levy,
A1 - D.R. Woodward,
PY - 1995
KW - software tools; C language; parallel programming; simulated annealing; circuit CAD; logic CAD; development systems; EDIF; software generation; FPGA; parallel microprocessors; codesign methods; hardware development tools; software tool; real-time parallel C code; scheduling theory; simulated annealing
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
M.J. Van Der Westhuizen, Dept. of Electr. Eng., Natal Univ., Durban, South Africa
R.G. Harley, Dept. of Electr. Eng., Natal Univ., Durban, South Africa
D.C. Levy, Dept. of Electr. Eng., Natal Univ., Durban, South Africa
D.R. Woodward, Dept. of Electr. Eng., Natal Univ., Durban, South Africa
With the advent of the FPGA and parallel microprocessors the need for practical codesign methods is becoming increasingly important. This paper proposes that codesign can be approached from existing hardware development tools. The paper also reports on the development of a software tool which uses EDIF to generate parallel, real-time C code. The view taken is that the problematic issues of codesign are the same as those for optimising general parallel processing systems and that scheduling theory is the foundation of both codesign and parallel design environments.
Index Terms:
software tools; C language; parallel programming; simulated annealing; circuit CAD; logic CAD; development systems; EDIF; software generation; FPGA; parallel microprocessors; codesign methods; hardware development tools; software tool; real-time parallel C code; scheduling theory; simulated annealing
Citation:
M.J. Van Der Westhuizen, R.G. Harley, D.C. Levy, D.R. Woodward, "Using EDIF for software generation," glsvlsi, pp.172, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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