Analyzing and verifying locally clocked circuits with the concurrency workbench

G
GLSVLSI
1995
Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Abstract - Analyzing and verifying locally clocked circuits with the concurrency workbench

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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	G. Baulch, D. Hemmendinger, C. Traver, "Analyzing and verifying locally clocked circuits with the concurrency workbench," Great Lakes Symposium on VLSI, pp. 144, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516041, author = {G. Baulch and D. Hemmendinger and C. Traver}, title = {Analyzing and verifying locally clocked circuits with the concurrency workbench}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {144}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516041}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Analyzing and verifying locally clocked circuits with the concurrency workbench SN - 1066-1395 SP EP A1 - G. Baulch, A1 - D. Hemmendinger, A1 - C. Traver, PY - 1995 KW - asynchronous circuits; timing; formal verification; process algebra; circuit analysis computing; logic CAD; logic design; locally clocked circuits; concurrency workbench; asynchronous communication; synchronous computational elements; concurrent system modelling; CCS process algebra; asynchronous circuits VL - 0 JA - Great Lakes Symposium on VLSI ER -

G. Baulch, Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA

D. Hemmendinger, Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA

C. Traver, Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516041

Locally Clocked Modules (LCMs) allow asynchronous communication between synchronous computational elements. The concurrency workbench models concurrent systems in the CCS process algebra. We describe the use of the concurrency workbench to specify, simulate, and verify implementations of LCMs and discuss its application to the specification of asynchronous circuits.

Index Terms:

asynchronous circuits; timing; formal verification; process algebra; circuit analysis computing; logic CAD; logic design; locally clocked circuits; concurrency workbench; asynchronous communication; synchronous computational elements; concurrent system modelling; CCS process algebra; asynchronous circuits

Citation:

G. Baulch, D. Hemmendinger, C. Traver, "Analyzing and verifying locally clocked circuits with the concurrency workbench," glsvlsi, pp.144, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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