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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Design and analysis of a low-power energy-recovery adder
The State University of New York at Buffalo
March 16-March 18
ISBN: 0-8186-7035-5
ASCII Text
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N. Tzartzanis, W.C. Athas, "Design and analysis of a low-power energy-recovery adder," Great Lakes Symposium on VLSI, pp. 66, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.
 
 
BibTex
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@article{ 10.1109/GLSV.1995.516026,
author = {N. Tzartzanis and W.C. Athas},
title = {Design and analysis of a low-power energy-recovery adder},
journal ={Great Lakes Symposium on VLSI},
volume = {0},
year = {1995},
issn = {1066-1395},
pages = {66},
doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516026},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Great Lakes Symposium on VLSI
TI - Design and analysis of a low-power energy-recovery adder
SN - 1066-1395
SP
EP
A1 - N. Tzartzanis,
A1 - W.C. Athas,
PY - 1995
KW - VLSI; CMOS logic circuits; delays; SPICE; circuit analysis computing; adders; integrated circuit design; logic CAD; circuit CAD; energy-recovery adder; SPICE simulation; energy dissipation; delay time; frequency range; CMOS logic circuits; VLSI
VL - 0
JA - Great Lakes Symposium on VLSI
ER -
 
N. Tzartzanis, Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
W.C. Athas, Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA
In this paper, an 8-bit energy-recovery adder design is evaluated through SPICE simulation for energy dissipation and delay time, and is compared against a supply-voltage-scaled adder. The experimental results indicate that the energy-recovery adder outperforms the supply-scaled version for a wide range of frequencies.
Index Terms:
VLSI; CMOS logic circuits; delays; SPICE; circuit analysis computing; adders; integrated circuit design; logic CAD; circuit CAD; energy-recovery adder; SPICE simulation; energy dissipation; delay time; frequency range; CMOS logic circuits; VLSI
Citation:
N. Tzartzanis, W.C. Athas, "Design and analysis of a low-power energy-recovery adder," glsvlsi, pp.66, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995
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