Optimizing wiring space in slicing floorplans

G
GLSVLSI
1995
Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Abstract - Optimizing wiring space in slicing floorplans

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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	J.T. Mowchenko, Y. Yang, "Optimizing wiring space in slicing floorplans," Great Lakes Symposium on VLSI, pp. 54, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516024, author = {J.T. Mowchenko and Y. Yang}, title = {Optimizing wiring space in slicing floorplans}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {54}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516024}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - Optimizing wiring space in slicing floorplans SN - 1066-1395 SP EP A1 - J.T. Mowchenko, A1 - Y. Yang, PY - 1995 KW - wiring; circuit optimisation; integrated circuit layout; circuit layout CAD; network routing; VLSI; wiring space optimisation; slicing floorplans; net density; sibling rectangles; circuit modules; branch and bound algorithm; heuristic; routed layouts; IC layout VL - 0 JA - Great Lakes Symposium on VLSI ER -

J.T. Mowchenko, Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada

Y. Yang, Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516024

This paper addresses the problem of minimizing wiring space in an existing slicing floorplan. Wiring space is measured in terms of net density, and the existing floorplan is adjusted only by interchanging sibling rectangles and by mirroring circuit modules. An exact branch and bound algorithm and a heuristic are given for this problem. Experiments show that both algorithms are effective in reducing wiring space in routed layouts.

Index Terms:

wiring; circuit optimisation; integrated circuit layout; circuit layout CAD; network routing; VLSI; wiring space optimisation; slicing floorplans; net density; sibling rectangles; circuit modules; branch and bound algorithm; heuristic; routed layouts; IC layout

Citation:

J.T. Mowchenko, Y. Yang, "Optimizing wiring space in slicing floorplans," glsvlsi, pp.54, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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