A scalable analog architecture for neural networks with on-chip learning and refreshing

G
GLSVLSI
1995
Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Abstract - A scalable analog architecture for neural networks with on-chip learning and refreshing

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Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)

The State University of New York at Buffalo

March 16-March 18

ISBN: 0-8186-7035-5

	ASCII Text	x
	B.A. Alhalabi, M. Bayoumi, "A scalable analog architecture for neural networks with on-chip learning and refreshing," Great Lakes Symposium on VLSI, pp. 33, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995.

	BibTex	x
	@article{ 10.1109/GLSV.1995.516020, author = {B.A. Alhalabi and M. Bayoumi}, title = {A scalable analog architecture for neural networks with on-chip learning and refreshing}, journal ={Great Lakes Symposium on VLSI}, volume = {0}, year = {1995}, issn = {1066-1395}, pages = {33}, doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516020}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Great Lakes Symposium on VLSI TI - A scalable analog architecture for neural networks with on-chip learning and refreshing SN - 1066-1395 SP EP A1 - B.A. Alhalabi, A1 - M. Bayoumi, PY - 1995 KW - analogue processing circuits; neural chips; learning (artificial intelligence); analogue storage; scalable analog architecture; neural networks; on-chip learning; on-chip refreshing; analog storage; analog functional blocks; analog pass switches; system versatility; learning speed; local analog synaptic updating scheme; unbounded scalability VL - 0 JA - Great Lakes Symposium on VLSI ER -

B.A. Alhalabi, Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

M. Bayoumi, Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516020

This paper discusses various techniques for analog storage and handling and proposes a new class of architecture suitable for modular and scalable analog neural networks with on-chip learning and refreshing. The new architecture is based on analog functional blocks and analog pass switches which enhance the system versatility. Supporting algorithms are also developed. A novel characteristic is the full-analog on-chip learning methodology which substantially increases the learning speed. The speedup is evidenced by the utilization of local analog synaptic updating scheme which utterly eliminates time-sharing components. Moreover, this localization scheme conceives unbounded scalability in this neural architecture.

Index Terms:

analogue processing circuits; neural chips; learning (artificial intelligence); analogue storage; scalable analog architecture; neural networks; on-chip learning; on-chip refreshing; analog storage; analog functional blocks; analog pass switches; system versatility; learning speed; local analog synaptic updating scheme; unbounded scalability

Citation:

B.A. Alhalabi, M. Bayoumi, "A scalable analog architecture for neural networks with on-chip learning and refreshing," glsvlsi, pp.33, Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), 1995

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