Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated signal-processing tasks are transformed in a SDR, including advanced compression algorithms, power control, channel estimation, equalization, and forward error control and protocol management. While there is a plethora of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and configurability. Amongst the more complex tasks performed in a high data rote wireless system is synchronization. This paper is about carrier and timing synchronization in SDRs using FPGA based signal processors. We describe and examine a QPSK Costas loop for performing coherent demodulation, and report on the implications of FPGA mechanization. Symbol timing recovery is addressed using a differential matched filter control system. A tutorial style approach is adopted to describe the operation of the timing recovery loop and considerations for FPGA implementation are outlined.