“RLOC” is the name given to a relational placement macro that is used to influence the layout of circuits that are realized on FPGAs using Xilinx's place and route software. This paper explores the thesis that modern FPGA architectures are powerful enough to no longer require the designer to provide a layout and that simulated annealing technology has advanced to the point that very good results can be obtained using no layout constraints at all. If this thesis is true then there is a profound effect on custom computing machines, which can be more easily, targeted from high-level specification languages like Handle-C and JHDL without requiring clumsy layout information to be accommodated at the language level.