Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems

F
FCCM
1999
Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Abstract - Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems

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	Similar Articles Articles by Milan Vasilko Articles by David Cabanis

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Napa California

April 21-April 23

ISBN: 0-7695-0375-6

	ASCII Text	x
	Milan Vasilko, David Cabanis, "Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 123, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.

	BibTex	x
	@article{ 10.1109/FPGA.1999.803674, author = {Milan Vasilko and David Cabanis}, title = {Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1999}, issn = {1082-3409}, pages = {123}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1999.803674}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems SN - 1082-3409 SP EP A1 - Milan Vasilko, A1 - David Cabanis, PY - 1999 VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

Milan Vasilko, Bournemouth University

David Cabanis, Bournemouth University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1999.803674

This paper presents a new approach to the simulation of Dynamically Reconfigurable Logic (DRL) systems, which offers better accuracy of modeling dynamic reconfiguration than previously reported simulation techniques. Our method, named Clock Morphing, is based on modeling dynamic reconfiguration via a reconfigured module clock signal, while using a dedicated signal value to indicate dynamic reconfiguration.We also discuss problems associated with the other DRL simulation techniques, describe the main principles of the proposed simulation method and evaluate its feasibility by implementing of a Clock Morphing based DRL simulation in VHDL.

Citation:

Milan Vasilko, David Cabanis, "Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems," fccm, pp.123, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999

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