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Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Elements for a Video Pipeline Processor
Napa California
April 21-April 23
ISBN: 0-7695-0375-6
ASCII Text
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Michael R. Piacentino, Gooitzen S. vanderWal, Michael W. Hansen, "Reconfigurable Elements for a Video Pipeline Processor," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 82, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.
 
 
BibTex
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@article{ 10.1109/FPGA.1999.803670,
author = {Michael R. Piacentino and Gooitzen S. vanderWal and Michael W. Hansen},
title = {Reconfigurable Elements for a Video Pipeline Processor},
journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on},
volume = {0},
year = {1999},
issn = {1082-3409},
pages = {82},
doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1999.803670},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
TI - Reconfigurable Elements for a Video Pipeline Processor
SN - 1082-3409
SP
EP
A1 - Michael R. Piacentino,
A1 - Gooitzen S. vanderWal,
A1 - Michael W. Hansen,
PY - 1999
VL - 0
JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on
ER -
 
Michael R. Piacentino, Sarnoff Corporation
Gooitzen S. vanderWal, Sarnoff Corporation
Michael W. Hansen, Sarnoff Corporation
This paper describes a family of reconfigurable processing elements (RPEs) used to support video processing for the Sarnoff Vision Front End 200 (VFE-200) vision system. Within the VFE-200 RPEs have been used to estimate visual motion, compute 3D scene structure using stereo analysis, perform geo-metric transformations (warps) on imagery with interpolation, and to act as triple ported frame store memory units. The RPEs described in this paper in-corporate complex DRAM memory control interfaces, high precision fixed- and floating-point arithmetic (including floating point division), and sophisticated hybrids of memory and computational functions. Within this paper, the architecture and implementation of the RPEs and the VFE-200 are described, and examples of how the RPEs are used to support specific computer vision functions at real-time video rates are presented.
Citation:
Michael R. Piacentino, Gooitzen S. vanderWal, Michael W. Hansen, "Reconfigurable Elements for a Video Pipeline Processor," fccm, pp.82, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 1999
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