FPGA based custom computing machine applications have grown tremendously. Reconfigurable FPGAs incur very less reconfiguration times and also have the ability to reconfigure partially. They provide avenues to reuse the hardware resources at runtime, thus decreasing the hardware costs. In this research, we present algorithms for temporal partitioning of applications into small size segments(under the area constraints), and scheduling of segments to ensure proper execution by satisfying the data dependencies among the segments. Our investigation concentrates on applications that are also directed acyclic graphs (DAGs). We have implemented the algorithms and have produced mappings of real applications on reconfigurable hardware.