A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure

F
FCCM
1998
IEEE Symposium on FPGAs for Custom Computing Machines
Abstract - A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure

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	Similar Articles Articles by Simon D. Haynes Articles by Peter Y.K. Cheung

IEEE Symposium on FPGAs for Custom Computing Machines

Napa Valley, California

April 15-April 17

ISBN: 0-8186-8900-5

	ASCII Text	x
	Simon D. Haynes, Peter Y.K. Cheung, "A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 226, IEEE Symposium on FPGAs for Custom Computing Machines, 1998.

	BibTex	x
	@article{ 10.1109/FPGA.1998.707900, author = {Simon D. Haynes and Peter Y.K. Cheung}, title = {A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1998}, issn = {1082-3409}, pages = {226}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1998.707900}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure SN - 1082-3409 SP EP A1 - Simon D. Haynes, A1 - Peter Y.K. Cheung, PY - 1998 VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

Simon D. Haynes

Peter Y.K. Cheung

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1998.707900

A design for a reconfigurable multiplier array is presented. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a conventional FPGA structure. The array can be configured to perform a number of 4n x 4m bit signed/unsigned binary multiplications. We have estimated that the FABs are about 25 times more efficient in area than the equivalent multiplier implemented using a conventional FPGA structure alone.

Citation:

Simon D. Haynes, Peter Y.K. Cheung, "A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure," fccm, pp.226, IEEE Symposium on FPGAs for Custom Computing Machines, 1998

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