On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

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5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97)

On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor (PDF)

Napa Valley, CA

April 16-April 18

ISBN: 0-8186-8159-4

	ASCII Text	x
	J. Cong, J. Peck, "On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 246, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), 1997.

	BibTex	x
	@article{ 10.1109/FPGA.1997.624629, author = {J. Cong and J. Peck}, title = {On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1997}, issn = {1082-3409}, pages = {246}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1997.624629}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor SN - 1082-3409 SP EP A1 - J. Cong, A1 - J. Peck, PY - 1997 KW - reconfigurable architectures; check tautology logic synthesis algorithm; FPGA based reconfigurable coprocessor; tautology checking; FPGA based reconfigurable application specific coprocessor; hardware accelerator implementation; application software interface; maximum speedup factor; Espresso II package VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

J. Cong, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA

J. Peck, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1997.624629

We summarize our study on implementing tautology checking, a fundamental logic synthesis algorithm, using an FPGA based reconfigurable application specific coprocessor. The use of the tautology checking algorithm is first discussed followed by the specifics of hardware accelerator implementation and interface to application software. We compare our hardware accelerator for the tautology check algorithm with the software implementation of the tautology check algorithm in Espresso II (R. Rudell and A. Sangiovanni-Vincentelli, 1987). Our experimental results show that our accelerator is capable of achieving a maximum speedup factor of 2.94 and averaging 1.36 on 110 modified industry benchmarks included with the Espresso II package.

Index Terms:

reconfigurable architectures; check tautology logic synthesis algorithm; FPGA based reconfigurable coprocessor; tautology checking; FPGA based reconfigurable application specific coprocessor; hardware accelerator implementation; application software interface; maximum speedup factor; Espresso II package

Citation:

J. Cong, J. Peck, "On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor," fccm, pp.246, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), 1997

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