Garp: a MIPS processor with a reconfigurable coprocessor

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	Similar Articles Articles by J.R. Hauser Articles by J. Wawrzynek

5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97)

Napa Valley, CA

April 16-April 18

ISBN: 0-8186-8159-4

	ASCII Text	x
	J.R. Hauser, J. Wawrzynek, "Garp: a MIPS processor with a reconfigurable coprocessor," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 12, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), 1997.

	BibTex	x
	@article{ 10.1109/FPGA.1997.624600, author = {J.R. Hauser and J. Wawrzynek}, title = {Garp: a MIPS processor with a reconfigurable coprocessor}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1997}, issn = {1082-3409}, pages = {12}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1997.624600}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Garp: a MIPS processor with a reconfigurable coprocessor SN - 1082-3409 SP EP A1 - J.R. Hauser, A1 - J. Wawrzynek, PY - 1997 KW - coprocessors; Garp Architecture; MIPS processor; reconfigurable coprocessor; reconfigurable machines; general-purpose computing; prototype software environment; performance; UltraSPARC; speedups; field programmable gate arrays; FPGA VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

J.R. Hauser, California Univ., Berkeley, CA, USA

J. Wawrzynek, California Univ., Berkeley, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1997.624600

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

Index Terms:

coprocessors; Garp Architecture; MIPS processor; reconfigurable coprocessor; reconfigurable machines; general-purpose computing; prototype software environment; performance; UltraSPARC; speedups; field programmable gate arrays; FPGA

Citation:

J.R. Hauser, J. Wawrzynek, "Garp: a MIPS processor with a reconfigurable coprocessor," fccm, pp.12, 5th IEEE Symposium on FPGA-Based Custom Computing Machines (FCCM '97), 1997

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