FPGA-based transformable computers for fast digital signal processing

F
FCCM
1995
IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95)
Abstract - FPGA-based transformable computers for fast digital signal processing

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	Similar Articles Articles by H.A. Chow Articles by H. Alnuweiri Articles by S. Casselman

IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95)

Napa Valley, California

April 19-April 21

ISBN: 0-8186-7086-X

	ASCII Text	x
	H.A. Chow, H. Alnuweiri, S. Casselman, "FPGA-based transformable computers for fast digital signal processing," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 0197, IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95), 1995.

	BibTex	x
	@article{ 10.1109/FPGA.1995.477426, author = {H.A. Chow and H. Alnuweiri and S. Casselman}, title = {FPGA-based transformable computers for fast digital signal processing}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7086-X}, pages = {0197}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1995.477426}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - FPGA-based transformable computers for fast digital signal processing SN - 0-8186-7086-X SP EP A1 - H.A. Chow, A1 - H. Alnuweiri, A1 - S. Casselman, PY - 1995 KW - signal processing; reconfigurable architectures; field programmable gate arrays; image processing; parallel algorithms; coprocessors; parallel architectures; matrix algebra; FPGA; transformable computers; fast digital signal processing; cost-effective; fast parallel arithmetic circuits; image processing; parallel convolution algorithm; transformable coprocessor; microprocessor system; reconfigurable architecture; convolutions; 8 bit VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

H.A. Chow, Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada

H. Alnuweiri, Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada

S. Casselman, Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1995.477426

Abstract: FPGA-based computing systems provide a feasible and cost-effective platform for implementing fast parallel arithmetic circuits for digital signal and image processing. This paper reports the results obtained from embedding a highly parallel convolution algorithm on an FPGA-based "transformable" computer. Such a computer is intended to serve as a transformable co-processor for a standard microprocessor system. However, the transformable co-processor is reconfigurable and is capable of exploiting the concurrency of computations more than the "sequential" microprocessor. Our experiments show that a significant gain in speed can be achieved by using the transformable coprocessor. We present an example of performing a sequence of (independent) 16-point convolutions on 8-bit data, and show that the speed factor improves significantly as the number of convolutions to be performed increases.

Index Terms:

signal processing; reconfigurable architectures; field programmable gate arrays; image processing; parallel algorithms; coprocessors; parallel architectures; matrix algebra; FPGA; transformable computers; fast digital signal processing; cost-effective; fast parallel arithmetic circuits; image processing; parallel convolution algorithm; transformable coprocessor; microprocessor system; reconfigurable architecture; convolutions; 8 bit

Citation:

H.A. Chow, H. Alnuweiri, S. Casselman, "FPGA-based transformable computers for fast digital signal processing," fccm, pp.0197, IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95), 1995

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