Architectural descriptions for FPGA circuits

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IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95)

Napa Valley, California

April 19-April 21

ISBN: 0-8186-7086-X

	ASCII Text	x
	S. Singh, "Architectural descriptions for FPGA circuits," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 0145, IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95), 1995.

	BibTex	x
	@article{ 10.1109/FPGA.1995.477420, author = {S. Singh}, title = {Architectural descriptions for FPGA circuits}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7086-X}, pages = {0145}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1995.477420}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Architectural descriptions for FPGA circuits SN - 0-8186-7086-X SP EP A1 - S. Singh, PY - 1995 KW - hardware description languages; field programmable gate arrays; logic arrays; architectural descriptions; FPGA circuits; FPGA-based synthesis roofs; hardware description language; circuit architecture; source level information VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

S. Singh, Dept. of Comput. Sci., Glasgow Univ., UK

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1995.477420

Abstract: FPGA-based synthesis roofs require information about behaviour and architecture to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices.

Index Terms:

hardware description languages; field programmable gate arrays; logic arrays; architectural descriptions; FPGA circuits; FPGA-based synthesis roofs; hardware description language; circuit architecture; source level information

Citation:

S. Singh, "Architectural descriptions for FPGA circuits," fccm, pp.0145, IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95), 1995

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