Design methodologies for partially reconfigured systems

F
FCCM
1995
IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95)
Abstract - Design methodologies for partially reconfigured systems

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	Similar Articles Articles by J.D. Hadley Articles by B.L. Hutchings

IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95)

Napa Valley, California

April 19-April 21

ISBN: 0-8186-7086-X

	ASCII Text	x
	J.D. Hadley, B.L. Hutchings, "Design methodologies for partially reconfigured systems," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 0078, IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95), 1995.

	BibTex	x
	@article{ 10.1109/FPGA.1995.477412, author = {J.D. Hadley and B.L. Hutchings}, title = {Design methodologies for partially reconfigured systems}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7086-X}, pages = {0078}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1995.477412}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Design methodologies for partially reconfigured systems SN - 0-8186-7086-X SP EP A1 - J.D. Hadley, A1 - B.L. Hutchings, PY - 1995 KW - reconfigurable architectures; logic partitioning; field programmable gate arrays; logic CAD; neural nets; design methodologies; partially reconfigured systems; run time reconfiguration; implementation approach; circuit modules; sequentially executed stages; separate circuit module; physical commonality; RTR application; design methodology; RRANN2; partial RTR artificial neural network VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

J.D. Hadley, Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA

B.L. Hutchings, Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1995.477412

Abstract: Run time reconfiguration (RTR) as an implementation approach that divides an application into a series of sequentially executed stages with each stage implemented as a separate circuit module. Partial RTR extends this approach by partitioning these stages and designing their circuit modules such that they exhibit a high degree of functional and physical commonality. Transitioning between configurations can then be accomplished by updating only the differences between configurations. This reduces the amount of time that an RTR application spends configuring and significantly enhances overall performance. The paper presents the design methodology for partial RTR in the context of RRANN2, a partial RTR artificial neural network.

Index Terms:

reconfigurable architectures; logic partitioning; field programmable gate arrays; logic CAD; neural nets; design methodologies; partially reconfigured systems; run time reconfiguration; implementation approach; circuit modules; sequentially executed stages; separate circuit module; physical commonality; RTR application; design methodology; RRANN2; partial RTR artificial neural network

Citation:

J.D. Hadley, B.L. Hutchings, "Design methodologies for partially reconfigured systems," fccm, pp.0078, IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95), 1995

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