Architecture of a FPGA-based coprocessor: the PAR-1

F
FCCM
1995
IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95)
Abstract - Architecture of a FPGA-based coprocessor: the PAR-1

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	Similar Articles Articles by J.M. Carrera Articles by E.J. Martinez Articles by S.A. Fernandez Articles by J.M.M. Chaus

IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95)

Napa Valley, California

April 19-April 21

ISBN: 0-8186-7086-X

	ASCII Text	x
	J.M. Carrera, E.J. Martinez, S.A. Fernandez, J.M.M. Chaus, "Architecture of a FPGA-based coprocessor: the PAR-1," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 0020, IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95), 1995.

	BibTex	x
	@article{ 10.1109/FPGA.1995.477405, author = {J.M. Carrera and E.J. Martinez and S.A. Fernandez and J.M.M. Chaus}, title = {Architecture of a FPGA-based coprocessor: the PAR-1}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7086-X}, pages = {0020}, doi = {http://doi.ieeecomputersociety.org/10.1109/FPGA.1995.477405}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Architecture of a FPGA-based coprocessor: the PAR-1 SN - 0-8186-7086-X SP EP A1 - J.M. Carrera, A1 - E.J. Martinez, A1 - S.A. Fernandez, A1 - J.M.M. Chaus, PY - 1995 KW - field programmable gate arrays; computer architecture; coprocessors; microprogramming; FPGA-based coprocessor; PAR-1; FPGA based coprocessor; programming methodology; sequencing models; irregular circuits; regular circuits; sorting network; speech recognition algorithm; architectural improvements; general FPGA based computing machines VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

J.M. Carrera, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain

E.J. Martinez, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain

S.A. Fernandez, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain

J.M.M. Chaus, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FPGA.1995.477405

Abstract: The implementation of a FPGA based coprocessor and its programming methodology are shown. The effects of different sequencing models, and regular and irregular circuits on the hardware and in the programming methodology are discussed. Two examples are described: a sorting network and the kernel of a speech recognition algorithm. The results are still preliminary but they suggest some architectural improvements for general FPGA based computing machines.

Index Terms:

field programmable gate arrays; computer architecture; coprocessors; microprogramming; FPGA-based coprocessor; PAR-1; FPGA based coprocessor; programming methodology; sequencing models; irregular circuits; regular circuits; sorting network; speech recognition algorithm; architectural improvements; general FPGA based computing machines

Citation:

J.M. Carrera, E.J. Martinez, S.A. Fernandez, J.M.M. Chaus, "Architecture of a FPGA-based coprocessor: the PAR-1," fccm, pp.0020, IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95), 1995

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