Formal Methods in Computer Aided Design (FMCAD'06) San Jose, California, USA November 12-November 16 ISBN: 0-7695-2707-8
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FMCAD.2006.1
We present a formal model of the bit transmission between registers with arbitrary clock periods. Our model considers precise timing parameters, as well as metastability. We formally define the behavior of registers over time. From that definition, we prove, under certain conditions, that data are properly transmitted. We discuss how to incorporate the model in a purely digital model. The hypotheses of our main theorem define conditions that must be satisfied by the purely digital part of the system to preserve correctness.
Citation:
Julien Schmaltz, "A Formal Model of Lower System Layers," fmcad, pp.191-192, Formal Methods in Computer Aided Design (FMCAD'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||