This paper describes LURU, a methodology for FPGA combinational technology mapping through the parallel search capability of Content-Addressable Memory (CAM). An overview is shown in Fig. 1. First, a circuit is partitioned into a set of subcircuits. Topologies of these subcircuits are described using textual string representations [(a) and (b) in Fig. 1]. A precomputed set of strings for the circuit topologies that can be contained in a LUT of K or fewer inputs [Fig. 1 (d)] can be matched against the circuit representation in parallel using the CAM shown in Fig. 1 (c). By using CAM, the search space is increased over traditional technology mapping algorithms. A final mapping is produced for an FPGA device consisting of a heterogeneous network of LUT?s of K or fewer inputs, shown in Fig. 1 (e).

Experimental results demonstrate that LURU can improve mapping quality by up to 49%, with an average of 21% improvement over traditional technology mapping techniques such as FlowMap and CutMap [9]. LURU exceeds the quality of such algorithms because LURU uses CAM to achieve a global search space. CAM?s are capable of both exact and inexact matching. Using inexact matching, it is possible to match approximately 96% of subcircuits to a set of 16 basic CSE?s [8].