Three-dimensional (3-D) integration is a promising technology [1] for reducing wire lengths in an integrated circuit. 3-D is especially attractive for FPGAs because the interconnect dominates their total area, delay, and power. Here, we design a 3-D FPGA that uses wafer bonding [2] to stack multiple programmable fabrics. Our results indicate that the area-delay product for a 5-layer 3-D FPGA reduces by 36% compared with that for a 2-D FPGA. Three-D technology also has some drawbacks, such as thermal issues because of increased power density. Analyzing these issues constitutes our next step towards designing 3-D FPGAs.