14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06) Open Source High Performance Floating-Point Modules Napa, California April 24-April 26 ISBN: 0-7695-2661-6
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2006.54
Given the logic density of modern FPGAs, it is feasible to use FPGAs for floating-point applications. However, it is important that any floating-point units that are used be highly optimized. This paper introduces an open source library of highly optimized floating-point units for Xilinx FPGAs. The units are fully IEEE compliant and acheive approximately 230 MHz operation frequency for doubleprecision add and multiply in a Xilinx Virtex-2-Pro FPGA (-7 speed grade). This speed is acheived with a 10 stage adder pipeline and a 12 stage multiplier pipeline. The area requirement is 571 slices for the adder and 905 slices for the multiplier.
Index Terms:
IEEE floating point, FPGA, reconfigurable computing
Citation:
K. Scott Hemmert, Keith D. Underwood, "Open Source High Performance Floating-Point Modules," fccm, pp.349-350, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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