Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms

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	Similar Articles Articles by Cao Liang Articles by Jing Ma Articles by Xinming Huang

14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06)

Napa, California

April 24-April 26

ISBN: 0-7695-2661-6

	ASCII Text	x
	Cao Liang, Jing Ma, Xinming Huang, "Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 339-340, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), 2006.

	BibTex	x
	@article{ 10.1109/FCCM.2006.47, author = {Cao Liang and Jing Ma and Xinming Huang}, title = {Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2661-6}, pages = {339-340}, doi = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2006.47}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms SN - 0-7695-2661-6 SP339 EP340 A1 - Cao Liang, A1 - Jing Ma, A1 - Xinming Huang, PY - 2006 KW - null VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

Cao Liang, University of New Orleans, New Orleans, LA

Jing Ma, University of New Orleans, New Orleans, LA

Xinming Huang, University of New Orleans, New Orleans, LA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2006.47

This paper presents hardware/software co-design architecture targeted on a single FPGA for two typical lattice decoding algorithms in MIMO system. Two levels of parallelisms are analyzed for an efficient implementation with the preprocessing part on embedded MicroBlaze soft processor and the decoder part on customized hardware. The system prototypes of the AV and VB decoders show that they support up to 34.2 Mbps and 3.15 Mbps data rate respectively on XUP Virtex-II pro developing board, which are 19 and 16 times faster than their respective implementations on a DSP.

Citation:

Cao Liang, Jing Ma, Xinming Huang, "Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms," fccm, pp.339-340, 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), 2006

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