The Quartz framework allows the generation of parametrised high-performance placed IP cores from higher level descriptions. Circuits are described in the Quartz language, which provides advanced features such as polymorphism, overloading, higher-order combinators and formal reasoning while supporting precise and flexible control of layout for efficient FPGA design. Our compiler transforms Quartz descriptions into VHDL libraries, maintaining design parametrisation and generating placement constraints to maximise performance, increasing clock frequency by up to 25%.