The achievement of effective implementations to multi-FPGA architectures is greatly dependent on the process of partitioning. Although several automated high-level partitioning (HLP) methods have been reported [2], most of them are designed to solve general partitioning problems, and tend to apply generic local optimization techniques that miss out on alternate formulations that become apparent only with knowledge of the algorithm?s functionality. The algorithmic formulation of discrete signal transforms (DST), especially that of the DFT, has been extensively studied. Automated computational algebra platforms for the algorithmic manipulation of fast transform algorithms have been proposed, as well as automated methods to optimize DST implementations to general purpose processor platforms [1]. However, these methods have yet to be successfully adapted to automated partitioning methodologies for dedicated distributed hardware platforms.