13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Los Alamitos April 18-April 20 ISBN: 0-7695-2445-1
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2005.9
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC?s 0.18?m CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic blocks and switch boxes. Test results demonstrate a throughput of 674 MHz at 1.8 V.
Citation:
David Fang, John Teifel, Rajit Manohar, "A High-Performance Asynchronous FPGA: Test Results," fccm, pp.271-272, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||