A High-Performance Asynchronous FPGA: Test Results

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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)

A High-Performance Asynchronous FPGA: Test Results (PDF)

Los Alamitos

April 18-April 20

ISBN: 0-7695-2445-1

	ASCII Text	x
	David Fang, John Teifel, Rajit Manohar, "A High-Performance Asynchronous FPGA: Test Results," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp. 271-272, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005.

	BibTex	x
	@article{ 10.1109/FCCM.2005.9, author = {David Fang and John Teifel and Rajit Manohar}, title = {A High-Performance Asynchronous FPGA: Test Results}, journal ={Field-Programmable Custom Computing Machines, Annual IEEE Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2445-1}, pages = {271-272}, doi = {http://doi.ieeecomputersociety.org/10.1109/FCCM.2005.9}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on TI - A High-Performance Asynchronous FPGA: Test Results SN - 0-7695-2445-1 SP271 EP272 A1 - David Fang, A1 - John Teifel, A1 - Rajit Manohar, PY - 2005 KW - null VL - 0 JA - Field-Programmable Custom Computing Machines, Annual IEEE Symposium on ER -

David Fang, Cornell University

John Teifel, Cornell University

Rajit Manohar, Cornell University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2005.9

We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC?s 0.18?m CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic blocks and switch boxes. Test results demonstrate a throughput of 674 MHz at 1.8 V.

Citation:

David Fang, John Teifel, Rajit Manohar, "A High-Performance Asynchronous FPGA: Test Results," fccm, pp.271-272, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005

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