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13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)
Los Alamitos
April 18-April 20
ISBN: 0-7695-2445-1
David Fang, Cornell University
John Teifel, Cornell University
Rajit Manohar, Cornell University
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC?s 0.18?m CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic blocks and switch boxes. Test results demonstrate a throughput of 674 MHz at 1.8 V.
Citation:
David Fang, John Teifel, Rajit Manohar, "A High-Performance Asynchronous FPGA: Test Results," fccm, pp.271-272, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005
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