13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05) Los Alamitos April 18-April 20 ISBN: 0-7695-2445-1
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2005.64
This paper proposes GAPLA: a Globally Asynchronous Locally Synchronous Programmable Logic Array architecture. The whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Data communications between synchronous blocks are controlled by 2-phase handshaking signals. The size and shape of each locally synchronous block are programmable so that different modules in a design can be effectively implemented. Each block could run at higher speed because only the fast local interconnections are used. Experimental results show an up to 28% performance improvement compared to the conventional FPGAs with small area overhead (around 2%).
Citation:
Xin Jia, Ranga Vemuri, "The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture," fccm, pp.291-292, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||