This paper presents a system-on-programmable chip approach for a Schnorr-Euchner strategy based sphere decoder. The decoding algorithm is partitioned with the division intensive matrix computation part on embedded microprocessor and the iterative lattice decoding function on programmable logics. Efficient hardware architectures are developed with three levels of parallelism. The system prototype of the decoder shows that it supports 35.75 Mbit/s data rate on an Altera Stratix EP1S10 FPGA located on Nios development board for a four antenna system with 16-QAM signal constellation, and is about 20 times faster than its implementation on a DSP.